Redundancy techniques are widely used in integrated circuit (semiconductor) memory devices, and other integrated circuit devices, to repair failed memory cells or circuits, in order to improve the device yields. Laser activated fuses are generally used to repair integrated circuits before packaging. Electrically activated fuses, also referred to herein as "electrical fuses", are generally used to repair a failed bit, a failed memory cell or other circuit after the integrated circuit has been packaged. Electrical fuses are also used to program the device for user and/or system requirements.
It is generally desirable for the electrical fuse to have a large current capacity so that it is not inadvertently activated (blown). Accordingly, the fuse is generally designed to have a high voltage and a large current capacity. When a polysilicon fuse or a polycide fuse is used, having a resistance value which ranges from several tens to several hundred ohms, a peak current of several tens to several hundred mA may be needed to reach a temperature of over 1300.degree. C. and thereby blow the fuse. See IEEE Transactions on Electron Devices, Vol. ED-29, No. 4, pp. 719-724, April 1982, entitled "Programming Mechanism of Polysilicon Resistor Fuses".
Unfortunately, since the current capability of an MOS transistor which is used as a switching element is generally determined by the ratio of gate width to gate length, the MOS transistor size increases in order to pass large currents. Since an integrated circuit often includes many electrical fuses, the need for large MOS transistors may cause an unwanted increase in the integrated circuit size. The layout of the electrical fuses also may generate unstable peak currents. These disadvantages may prevent the widespread use of electrical fuses in integrated circuit devices.
A known fuse circuit for reading and programming a fuse is disclosed in U.S. Pat. No. 4,517,583, the structure of which is shown herein at FIG. 1. The fuse circuit includes a load PMOS transistor 1 which is connected between a power supply terminal Vpp/Vcc and an output terminal Vout, and has its gate connected to program/read control signals .phi.P/.phi.R. Fuses F1 to Fn are connected in parallel to the output terminal Vout, and fuse select transistors S1 to Sn are connected between each of the fuses and a source line 2, which have their respective gates connected to program/read voltages G1 to Gn. The source line 2 is connected to ground potential Vss (or a substrate voltage).
A single electrical fuse cell is comprised of a single fuse and a single fuse select transistor. For example, upon programming of the fuse F1, a program current supplied from the power source terminal Vpp/Vcc through the load PMOS transistor 1, passes through the fuse F1 and flows to ground potential Vss through the fuse select transistor S1 having the program/read voltage G1 applied to the gate thereof. The temperature in the fuse F1 is raised due to the large amount of current flowing through the fuse F1. As a result, the fuse F1 is blown and the programming operation is completed. During programming, program/read voltages G2 to Gn of 0 volts are applied to the gates of the remaining fuse select transistors S2 to Sn, so that the fuses F2 to Fn corresponding to the fuse select transistors S2 to Sn are not blown.
After programming, a reading operation for reading whether the fuse is blown is performed. At the output terminal Vout, the current path formed through the fuse F1, which is selected by the read voltage supplied from the power source terminal Vpp/Vcc and the program/read voltage G1 applied to the gate of the selected fuse select transistor S1, is detected. The read voltage during the read operation is lower than the programming voltage, in order to prevent an undesired programming of fuses and variation of fuse characteristics.
Unfortunately, in the circuit structure of FIG. 1, a single fuse select transistor for a fuse is employed in the programming and reading operations. The size of the fuse select transistor accordingly increases, in order to pass a large amount of current for programming. The large size of the transistor is not generally needed during the reading operation.
FIG. 2 is a circuit diagram illustrating another conventional fuse circuit, in which separate circuits for programming and reading are provided. In addition to the circuit components of FIG. 1, FIG. 2 includes a read load PMOS transistor 3 which is connected between a power source terminal Vcc and an output terminal Vout, and has its gate connected to the read control signal .phi.R. Read fuse select transistors R1 to Rn are disposed parallel to program fuse select transistors S1 to Sn, and are each connected between the fuses and ground potential Vss. A single electrical fuse cell 5 is comprised of a single fuse, a single program fuse select transistor and a single read fuse select transistor. The read fuse select transistors R1 to Rn may be smaller than the program fuse select transistors S1 to Sn. The programming operation of FIG. 2 is generally the same as that of FIG. 1. In the reading operation, however, the current flowing through the selection of the read fuse select transistor R1, for example, is detected in the output terminal Vout.
The circuit structure of FIG. 2 can overcome problems including the reliability of the fuses and the control of the amount of current, which may not be solved by the circuit of FIG. 1. However, since read fuse select transistors are used in addition to the large program fuse select transistors, a large layout size is generally needed for the fuse select transistors, and the suppression of peak current generated by the large program fuse select transistors may be difficult.